Parallel Data Processing Solutions for Software Defined Radio
Keywords:
Software Defined Radio, Parallelism, Digital Signal Processing, Tensor Processing Unit, Systolic-Type ArrayAbstract
Taking into consideration the decisions behind the current day processors used for Software Defined Radio (SDR) and digital signal processing, we will examine how current machine learning chips, such as Tensor Processing Units or their components including Systolic Arrays and Matrix Multiplier Units, can be incorporated into signal processing today. There are several architectural approaches to implementing digital signal processing with SDR, ranging from Field Programmable Gate Arrays to General Purpose Processors and Digital Signal Processors. SDR has historically been developed to move algorithms and signal processing away from hardware that is built for a specific purpose to software that can accommodate new algorithms and processes with ease. Recently, there have been advances in leveraging data level parallelism for SDR, including the use of Graphics Processor Units. After consideration of current and previous SDR technology, we propose a hypothetical Dynamic Band Processing Unit X (DBPUX) for processing multiple bands per cycle in a Digitize at Intermediate Frequency (DIF) SDR architecture using a Matrix Multiplier Unit (MMU) and a Systolic-Type Array for specific signal processing tasks. Further work is needed to simulate and apply performance metrics to the proposed processor.
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